1. Field of the Invention
The invention relates in general to circuit simulation and in particular to a method for re-simulating a selected portion of a circuit during a selected subinterval of the simulation time of a previous simulation of the entire circuit.
2. Description of Related Art
A digital circuit designer initially uses a high level language to model the logic to be carried out by an integrated circuit. Using various computer-aided design tools, the designer converts the high level language (HDL) description of the circuit into progressively lower level designs, until the circuit design is sufficiently detailed to guide IC fabrication. At each step of the process, the designer can use a computer-based circuit simulator to test the circuit design by programming the simulator with an input “testbench” derived from a netlist description of the circuit design and a description of the time-varying behavior of the circuit's input signals. A netlist can describe the circuit as being formed by instances of standard cells such as transistors, gates and passive devices communicating through signals conveyed by conductors (“nets”) interconnecting the cell instances. A cell library provides detailed behavioral models of the standard cells the simulator can use to evaluate behavior of cell instances. As the design progresses to the layout stage, where cell instance positions and net routes are established, the simulator evaluates models of the nets to accurately account for path delays in the nets.
A simulator treats time as an independent variable. To carry out a simulation, the simulator must therefore remember the state of every signal it computes during each simulation time at least long enough to compute the state of each signal during the next simulation time. However, to enable a designer to determine how various circuit signals behaved during the simulation, a simulator must generate and save simulation data indicating times at which those signals change state and the state to which they change. Since the amount of simulation data a computer-based simulator generates during a simulation is usually much too large to retain in a computer's random access memory, a simulator will temporarily halt its simulation from time-to-time and perform a simulation data “dump” by writing the simulation data it has accumulated in memory to a hard disk or other bulk storage device. Since hard disk accesses require substantial amounts of time, the time a simulator needs to dump the simulation data to a hard disk often constitutes a substantial portion of the total amount of time it needs to perform a simulation.
A designer can reduce simulator processing time by reducing the amount of data the simulator must save to a hard disk during the simulation. One way to do that is program a simulator to initially simulate a circuit with no simulation data dump but to internally monitor simulation results and to report any detected failures or errors. When an error is reported, the designer can then program the simulator to re-simulate the entire full simulation data dump to enable the designer to debug the circuit. The main drawback to this approach is the slow turnaround time for the second simulation since the simulation must restart from the beginning of the full simulation interval.
In a prior art “checkpoint” approach to simulation, a simulator saves “checkpoint data” only after every J nanoseconds of simulation time representing a “snapshot” of the current state of every signal at that simulation time, as well as other data needed to fully describe the state of the simulator at that simulation time, and refrains from saving a complete record of every signal state change. FIG. 1 is a timing diagram illustrating circuit signal states as functions of time. Vertical dashed lines indicate times for which the simulator saves snapshot data indicating signal states, where in this example, J=100. The snapshot data indicates an error, designated by an “x”, occurred in signal S6 at times 400, 500 and 600 and in other signals at times 500 and 600. Since the amount of data needed to represent the state of the simulator and every signal after every 100 nanoseconds of simulation time can be much smaller that the amount of simulation data describing all signal state changes, the simulator need not write checkpoint data to the hard disk as often, and the simulation can progress more quickly.
Since errors tend to propagate from one signal to another in a circuit, an error that occurs between checkpoints is likely to cause an error in one or more signals at the next checkpoint. For example, the true source of the error in the state of signal S6 observed at simulation time 400 may be an error in setting the state of some other signal at an earlier time that affected the state of signal S6 at time 400. When the simulator provides the designer with snapshot data only for times 300 and 400, the designer will not be able to directly determine whether any signal errors occurred between times 300 and 400. However, the designer can program the simulator to re-simulate the entire circuit between times 300 and 400 as illustrated in FIG. 2, with the simulator providing data completely describing behavior of every signal between times 300 and 400 so that the simulator maintains a complete record of all signal behavior during that time, rather than just a snapshot of signal states acquired at selected checkpoints. As shown in FIG. 2 the designer can then see from the complete data record that errors begin to occur, for example, at time 325 with an error in a signal S7. The designer might then investigate the possibility of an error in logic or timing of the portion of the circuit producing signal S7 at time 325.
The simulator need not repeat the simulation from time 0 because the snapshot data it saved at time 300 fully describes the state of the circuit at that time, allowing the designer to program the simulator to initialize the circuit to that state when it carries out the re-simulation starting at time 300.
The checkpoint approach can reduce simulator processing time, but periodically saving snapshot data indicating states of all signals of a circuit during the simulation even for every Nth nanosecond can still be time-consuming. Re-simulation can start only from one of a set of pre-selected simulation times at which snapshot data rather from any desired simulation time. Limiting the number of checkpoints to reduce simulation time can substantially increase re-simulation processing time.
A netlist typically organizes a circuit design into hierarchy of modules that communicate with one another through signals that cross module boundaries, wherein each module residing at any level of the design is formed by a collection of cells and/or modules residing at a lower level of the design. For example FIG. 3 depicts a circuit design at a hierarchical level including eight modules M1-M8 communicating with one another through signals. U.S. Pat. No. 6,321,363 issued Jan. 11, 1999 to Huang teaches to reduce simulation interval by saving data only for the signals that pass between modules at a selected level of the design hierarchy while refraining from saving simulation data for signals that are wholly internal to a single module. Since a typical module will have a much larger number of internal signals than input and output signals, a simulator can substantially reduce processing time by saving simulation data only for module input and output signals. When, for example, a designer determines from the saved simulation data that an error in an output signal of module M3 occurred at some particular time, but that all of that module's input signals were correct up to that time, the designer will suspect that there is an error in the design of module M3. To obtain a more detailed view of the internal behavior of module M3, the designer can reprogram the simulator to re-simulate the behavior of only that module up to the time at which the module output signal error is detected, with the simulator saving simulation data for all of that module's signals, including not only its input and output signals but also its internal signals. In creating a testbench for programming the simulator to simulate only module M3, the designer can derive a description of the time-varying behavior of the signals that particular module receives from other modules M2, M4 and M5 from the simulation data the simulator saved during the initial full-circuit simulation.
When circuit includes devices such as RAMs, ROMs, latches, registers, flip-flops and the like for storing data and thereafter producing output signals representing the stored data, the response of a module to its input signals at any time during a simulation depends not only on its internal architecture, but also on the state of the data it currently stores in such memories. To reduce re-simulation time, a designer might like to program the simulator to re-simulate module M3 only during a limited interval of N nanoseconds of simulation time immediately preceding the time K in which the error in one of its output signals appeared, but the designer cannot do so without specifying the states of the module's internally stored data at time K-N. However since the data representing input and output signals of module M3 do not reflect the state of all its stored data, the designer cannot derive the information needed to properly initialize the state of module M3 at time K-N. The designer must therefore program the simulator to re-simulate module M3 from simulation time 0, where initial states of the module's stored data are known, rather than from time K-N.
What is needed is a way to reduce simulator processing time by requiring a simulator to save simulation data for only a selected portion of a simulated circuit's signals, but which provides enough information about signal states during the simulation to permit re-simulation of any selected subcircuit spanning any selected portion of the full simulation interval.